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Open source

PUBLIC REPOSITORIES / REVIEWABLE

Work you can read before you engage us.

We do not publish client names or project outcomes. These repositories are the part of our engineering that can be shown in full: source, tests, CI configuration, and licence.

Each entry below states what the project contains and what it does not claim, taken from the repository's own documentation. Nothing here is a benchmark result or a maturity rating we have assigned ourselves.

Repositories4AUTHORED BY SVC
Commits332ACROSS ALL FOUR
LicencesMIT / Apache-2.0OSI APPROVED
Forks listed0OWN WORK ONLY
OSS.01MIT

kvips

Vendor-neutral UVM verification IP for AMBA protocols.

SystemVerilog / UVM · 93 COMMITS · SINCE JANUARY 2026

Repository Documentation

What it contains

  • AXI4 Full, APB (APB3/APB4 selectable at runtime) and AHB-Lite agents.
  • SVA protocol checkers with scoreboard-backed example environments.
  • Verilator regressions running in GitHub Actions on the AXI4, APB and AHB suites.
  • Example run scripts for Questa, VCS and Xcelium.

What it does not claim

  • All three VIPs are marked example-tested at v0.1; AHB Full is partial.
  • PCIe and USB 3.x are roadmap entries with no implementation in the repository.
  • The commercial simulator flows are examples, to be validated in your own environment.

SUPPORTS IP Verification →

OSS.02Apache-2.0

sisrv-platform

An RV32IMAC SoC platform with its verification and synthesis flow.

SystemVerilog / Assembly / Python · 129 COMMITS · SINCE MARCH 2026

Repository

What it contains

  • RV32IMAC core: in-order pipeline, machine and user mode, 8-region PMP, CSRs and precise traps.
  • Platform: ROM, RAM, CLINT, PLIC, GPIO, UART, an internal corebus and an optional AXI4-Lite bridge.
  • Debug: RISC-V Debug Module 0.13 subset over JTAG, with two hardware triggers.
  • Verification: 76 assembly regression tests, 43+ cocotb tests, four formal proof sets, and RISCOF architectural tests at 95/95 on the I/M/C subset.
  • Synthesis: Yosys with Sky130 static timing analysis.

What it does not claim

  • Not a certified or licensable commercial RISC-V IP product.
  • No cache, and no physical GDS sign-off.
  • Benchmark figures in the repository are internal cycle-normalized Verilator measurements, not certified EEMBC submissions.

SUPPORTS RISC-V Verification →

OSS.03Apache-2.0

sentinel-dv

An MCP server giving AI agents read-only access to verification artifacts.

Python · 87 COMMITS · SINCE JANUARY 2026

Repository

What it contains

  • Model Context Protocol server exposing verification results through a typed, schema-driven interface.
  • Reads UVM, cocotb and SystemVerilog assertion and coverage output.
  • Waveform summaries parsed from .wave.json and .vcd files.
  • Secret redaction and deterministic outputs.

What it does not claim

  • Read-only by design: it does not drive or control simulators.
  • No raw FSDB or WLF streaming.

SUPPORTS EDA DevOps →

OSS.04Apache-2.0

sentinel-ci

An MCP server giving AI agents read-only access to CI/CD data.

Python · 23 COMMITS · SINCE JANUARY 2026

Repository

What it contains

  • One interface over Jenkins, GitHub Actions and GitLab CI.
  • Secret redaction across credential, token and key patterns.
  • Audit logging of operations.

What it does not claim

  • Read-only by default: no build triggers and no configuration changes.
  • Covers Jenkins, GitHub Actions and GitLab CI only.
  • The least developed of these four by commit history.

SUPPORTS EDA DevOps →

Scope of this pageWHAT IS AND IS NOT HERE

Why the list is short.

A longer list would be easy to produce and would mean less.

  1. 01Only repositories authored here are listed. Forks of other people's projects stay out, however useful they are to us.
  2. 02Only work related to our published services is listed. Unrelated experiments are not evidence of verification capability.
  3. 03Capability statements are quoted from each repository, including the limits each one places on itself.
  4. 04Every claim on this page can be checked against the linked source, its commit history and its CI runs.
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